1. Field of the Invention
The present invention relates to digital division of electrical signals by both integer and fractional division ratios. Fractional division is particularly important in digital data transmission and in the transmission of digitized voice, both of which are clocked from a common timing source and which require a plurality of lower frequency rates, some of which may be fractional rates.
2. Description of the Prior Art
Digital divider circuits of the prior art typically are capable of whole integer binary or decade division of an electrical signal into a plurality of divided down signals at lower frequency rates. An example of a conventional whole number digital divider is a standard synchronous presettable binary counter such as the Fairchild Semiconductor 54F/74F161A or 54F/74F163A high-speed synchronous modulo-16 binary counters. This standard component has the capability of receiving an input clock and generating lower frequency clocks at 1/2, 1/4, 1/8, and 1/16 the input clock frequency. This prior art synchronous presettable counter also enables the presetting of selectable states out of the normal order to obtain various combinations of whole integer division of an input timing signal.
It is also known in the prior art that by changing the phase of the incoming timing signal that the clock rate will be affected. Various circuits utilizing a plurality of digital components have been devised in the known prior art to accomplish digital division by a fractional number. All of the known prior art techniques involve complex logic circuitry having a large number of components and tend to result in assymetric signals after the fractional division is accomplished; that is, instead of a well defined squarewave or near squarewave, the fractionally divided down signal may consist of logic pulses of approximately 20% up (high) and 80% down (low) or vice versa.
In the prior art, separate circuits are used, for example, for a divide-by-4 and divide-by-4.5 operation. The divide-by-4 circuit can be a standard 2-bit counter available off-the-shelf while the divide by 4.5 circuit may typically consist of a 5-bit Johnson counter whose fifth bit is used to control the counter through other logic circuitry such that the count is shortened by a 1/2 clock period each 5 counts, causing the Johnson counter to divide by 9 instead of the normal 10.
It is, therefore, an object of the present invention to provide a simple digital circuit for effecting fractional digital division of an incoming timing or clock signal with a selectable division ratio, low power dissipation, and a substantially reduced number of electrical components.
It is an additional object of the present invention to obtain a fractional divided down output signal as close to symmetric as possible. Such symmetry is important in data transmission; particularly for a timing signal, since the sampling edge of a clock should be approximately in the center of the data pulse to be sampled, otherwise noise rather than data could be sampled.